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october 2010 doc id 16524 rev 2 1/23 23 stpms1 dual-channel 1-bit, 2 mhz, 1 st order sigma-delta modulator with embedded pga features v cc supply range: 3.2 v - 5.5 v two 1 st order sigma-delta modulators programmable chopper- stabilized low noise and low offset amplifier supports 50-60 hz ac watt meters internal low-drop regulator at 3 v (typ.) precision voltage reference: 1.23 v and 30 ppm/c (typ.) applications power metering motor control industrial process control weight scale pressure transducers description the stpms1, also called a smart-sensor device, is an assp designed for effective measurement in power line systems utilizing the rogowski coil, current transformer, or shunt principle. it is used in combination with the stpmc1 programmable poly-phase energy calculator ic, as a building block for single-phase or poly-phase energy meters. the stpms1 is a mixed signal ic consisting of an analog and a digital section. the analog section consists of a pre-amplifier and two 1 st order ? modulator blocks, band-gap voltage reference, a low-drop voltage regulator, and dc buffers, while the digital section consists of a clock generator and output multiplexer. this device is designed for use in medium resolution measurement applications when single or double inputs must be monitored at the same time. qfn16 (3 x 3 mm.) table 1. device summary order code package packaging STPMS1BPQR qfn16 (3 x 3 mm) 2500 parts per reel www.st.com
contents stpms1 2/23 doc id 16524 rev 2 contents 1 schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.1 conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.2 notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 typical performance characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8 theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.1 general operation description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.2 function description of the analog part . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.3 functional description of the digital part . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
stpms1 schematic diagram doc id 16524 rev 2 3/23 1 schematic diagram figure 1. block diagram cip cin vip vin vcc pga 8x, 32x 1 st ord modulator 1 st ord ? modulator ldo vdd gnd bias ref digital front end ms1 clk dat ms0 datn ? am07830v1 cip cin vip vin vcc pga 8x, 32x 1 st ord modulator 1 st ord ? modulator ldo vdd gnd bias ref digital front end ms1 clk dat ms0 datn ? am07830v1
pin configuration stpms1 4/23 doc id 16524 rev 2 2 pin configuration figure 2. pin connection (top view) 1 gnd vddac gnd ms0 vddd vdd ms1 vddav vcc datn clk dat vin cin cip vip gnd am07831v1 1 gnd vddac gnd ms0 vddd vdd ms1 vddav vcc datn clk dat vin cin cip vip gnd am07831v1 table 2. pin description pin symbol description 1 vdd + 3.0 v output of ldo 2 gnd ground level for signals and pin protection 3 vddac current channel modulator supply input 4 gnd ground level for signals and pin protection 5 cip current channel + 6 cin current channel - 7 vip voltage channel + 8 vin voltage channel - 9 vddav voltage channel modulator supply input 10 vddd digital front-end supply input 11 ms0 input for configurator 0 12 ms1 input for configurator 1 13 clk input for external measurement clock 14 dat output of multiplexed ? signal 15 datn output of multiplexed ? signal negated 16 vcc unregulated supply voltage exp pad gnd ground level for signals and pin protection
stpms1 electrical characteristics doc id 16524 rev 2 5/23 3 electrical characteristics note: absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. table 3. absolute maximum ratings symbol parameter value unit vcc dc input voltage -0.3 to 6 v i pin current on any pin (sink/source) 150 ma v id input voltage at digital pins (ms0, ms1, clk, dat, datn) -0.3 to v cc +0.3 v v ia input voltage at analog pins (vip, vin, cip, cin) -0.7 to 0.7 v esd human body model (all pins) 3.5 kv t op operating ambient temperature -40 to 85 c t j junction temperature -40 to 150 c t stg storage temperature range -55 to 150 c table 4. thermal data symbol parameter value unit r thja thermal resistance junction-ambient 38.10 (1) c/w 1. this value refers to a single-layer pcb, jedec standard test board.
general operating conditions stpms1 6/23 doc id 16524 rev 2 4 general operating conditions v cc = 5 v, t a = 25 c, 2.2 f between v dd and gnd, 100 nf between v cc and gnd, f clk = 2.048 mhz unless otherwise specified. table 5. general operating conditions symbol parameter test conditions min. typ. max. unit general section v cc operating supply voltage 3.165 5.5 v i cc quiescent current 1.049 mhz; v cc =3.165 v; c l =100 nf, no loads 2.5 ma v por power on reset on v cc 2.5 v v dd regulated supply voltage 1.049 mhz; v cc =3.2 v; c l =100 nf, no loads 2.85 3.00 3.15 v i latch current injection latch-up immunity 300 ma f clk nominal frequencies 1.0 2.458 mhz dc measurement accuracy resolution 11 16 bit inl integral non-linearity result referred to a 13-bit resolution of cip- cin channel 0.35 lsb result referred to a 9-bit resolution of vip- vin channel 0.5 dnl differential linearity result referred to a 13-bit resolution of cip- cin channel 0.2 lsb result referred to a 9-bit resolution of vip- vin channel 0.4 offset error result referred to a 13-bit resolution of cip- cin channel 0.15 lsb result referred to a 9-bit resolution of vip- vin channel 0.05 gain error result referred to a 13-bit resolution of cip- cin channel 0.05 lsb/ v result referred to a 9-bit resolution of vip- vin channel 0.001 nf noise floor cip-cin channel, gain 8x 115 db psrr dc power supply dc rejection voltage signal: 200 mv rms /50 hz current signal: 10 mv rms /50 hz f clk = 2.048 mhz v cc =3.3 v10 %, 5 v10 % 0.2 %
stpms1 general operating conditions doc id 16524 rev 2 7/23 symbol parameter test conditions min. typ. max. unit ac measurement accuracy snr signal to noise ratio cip-cin channel ? vin=120 mv @ 55 hz gain 8x 65 db vip-vin channel ? vin=230 mv @ 55 hz 50 sinad signal to noise ratio + distortion cip-cin channel ? vin=120 mv @ 55 hz gain 8x 65 db vip-vin channel ? vin=230 mv @ 55 hz 50 thd total harmonic distortion cip-cin channel ? vin=120 mv @ 55 hz gain 8x -80 db vip-vin channel ? vin=230 mv @ 55 hz -70 sfdr spurious free dynamic range cip-cin channel ? vin=120 mv @ 55 hz gain 8x 80 db vip-vin channel ? vin=230 mv @ 55 hz 50 psrr ac power supply ac rejection voltage signal: 200 mv rms /50 hz current signal: 10 mv rms /50 hz f clk = 2.048 mhz v cc =3.3 v+0.2 v rms 1 @100 hz v cc =5.0 v+0.2 v rms 1 @100 hz 0.1 % analog inputs (cip, cin, vip, vin) v max maximum input signal levels vip-vin channel -0.3 +0.3 v cip-cin channel gain 8x gain 32x -0.15 -0.035 +0.15 +0.035 v f spl a/d sampling frequency f clk /2 hz v off amplifier offset 20 mv z ip vip, vin impedance over the total operating voltage range 200 400 k z in cip, cin impedance over the total operating voltage range 240 k g err current channel gain error 10 % i ilv voltage channel leakage current v cc = 5.3 v, f clk = 1.049 mhz -1 1 a i ili current channel leakage current -1 1 input enabled -10 10 digital i/o (clk, dat, datn, ms0, ms1) v ih input high voltage 0.75 v cc 5.3 v v il input low voltage -0.3 0.25v cc v table 5. general operating conditions (continued)
general operating conditions stpms1 8/23 doc id 16524 rev 2 clk - clock signal on clk pin clk sample - sigma-delta sample frequency bsv - sigma-delta bitstream of voltage signal bsc - sigma-delta bitstream of current signal data - multiplexed data of voltage and current signal on dat pin symbol parameter test conditions min. typ. max. unit v oh output high voltage i o =-1 ma, c l =50 pf, v cc =3.2 v v cc - 0.4 v v ol output low voltage i o =+1 ma, c l =50 pf, v cc =3.2 v 0.4 v i up pull up current 15 a t tr transition time c load =50 pf 10 ns t l latency from 50 % of clk to 50 % to dat 40 ns clock input f clk nominal frequencies low precision 1.0 1.228 mhz high precision 2.0 2.458 mhz on chip reference voltage v ref reference voltage 1.21 1.23 1.25 v t c temperature coefficient after calibration 30 50 ppm/ c table 5. general operating conditions (continued) figure 3. timing diagram am07832v1 am07832v1
stpms1 application doc id 16524 rev 2 9/23 5 application the choice of external components in the transduction section of the application is a crucial point in the application design, affecting the precision and the resolution of the whole system. among the several considerations, a compromise must be found between the following needs: 1. maximize the signal to noise ratio in the voltage and current channel 2. choose the current to voltage conversion ratio ks and the voltage divider ratio in a way that calibration can be achieved (see also the an2299; fast digital calibration procedure for stpm01 based energy meters , application note) 3. choose ks to take advantage of the whole current dynamic range according to desired maximum current and resolution. to maximize the signal to noise ratio of the current channel the voltage divider resistors ratio should be as close as possible to that shown in ta bl e 6 . figure 4 below shows a reference schematic for an application with the following properties: p = 64000 imp/kwh inom = 5 a imax = 60 a typical values for the current sens ors sensitivity are indicated in ta bl e 6 . figure 4. timing diagram am07833v1 am07833v1
application stpms1 10/23 doc id 16524 rev 2 note: the above listed components refer to typical metering applications. however, stpms1 operation is not limited to the choice of these external components. table 6. suggested external components in metering applications function component description value tolerance unit calculator stpmc1 --- --- --- --- line voltage interface resistor divider r to r ratio v rms =230 v 1:1650 1 % 50 ppm/c v/v r to r ratio v rms =110 v 1:830 line current interface rogowski coil current to voltage ratio k s 0.15 5 % 50 ppm/c mv/a ct 1.7 5 % shunt 0.43 5 % figure 5. simplified application schematics for stpmc1 based energy metering am07834v1 am07834v1
stpms1 application doc id 16524 rev 2 11/23 figure 6. connection schematic for dsp based applications ms0 cin cip ms1 dat datn clk gnd vdd vcc sensor 1 sensor 2 vip vin anti aliasing network anti aliasing network clkout datin dsp am07835v1 ms0 cin cip ms1 dat datn clk gnd vdd vcc sensor 1 sensor 2 vip vin anti aliasing network anti aliasing network clkout datin dsp am07835v1
terminology stpms1 12/23 doc id 16524 rev 2 6 terminology 6.1 conventions the lowest analog and digital power supply voltage is named gnd which represents the system ground. all voltage specifications for digital input/output pins are referred to gnd. positive currents flow into a pin. sinking current means that the current is flowing into the pin and then it is positive. sourcing current means that the current is flowing out of the pin and then it is negative. timing specifications of a signal treated by a digital control part are relative to clk. this signal is provided from the stpmc1 calculator ic of 1.024 mhz or of 2.048 mhz nominal frequency. a positive logic convention is used in all equations. 6.2 notation current and voltage signals are represented as u and i.
stpms1 typical performance characteristics doc id 16524 rev 2 13/23 7 typical performance characteristics figure 7. snrh of cip-cin channel, gain 32x fi gure 8. snhr of cip-cin channel, gain 8x figure 9. snhr of vip-vin channel figure 10. sinad of cip-cin channel, gain 32x figure 11. sinad of cip-cin channel, gain 8x figure 12. sinad of vip-vin channel
typical performance characteristics stpms1 14/23 doc id 16524 rev 2 figure 13. relative gain error of cip-cin channel, gain 32x figure 14. relative gain error of cip-cin channel, gain 8x figure 15. relative gain error of vip-vin channel figure 16. accuracy over dynamic range
stpms1 theory of operation doc id 16524 rev 2 15/23 8 theory of operation 8.1 general operation description the stpms1 performs first-order analog modulation of signals which have frequencies varying from dc to 2 khz on two independent channels in parallel. there is a current channel for measuring line current and a voltage channel for measuring line voltage. the outputs of the converters provide two streams of digital ones and zeros which are therefore multiplexed in time to reduce the number of external connections. the sampling and the data multiplexing are driven by an external clock signal, as it is used to strobe the analog inputs. the combination of one or more stpms1s and an stpmc1 (which implements the digital filtering) constitutes a conversion system for energy metering applications. the stpms1 can also be used along with a dsp programmed to demultiplex the output bitstream and to implement the digital filtering as a medium resolution adc system. when used in energy metering applications, the voltage channel is connected externally and differentially to a line voltage divider which provides an analog signal proportional to the voltage u. the current channel is connected to a rogowski coil, or to a current transformer (ct) or a shunt, which are used to interface the line current. the rogowski coil provides an analog signal proportional to di/dt, while the shunt or ct provides an analog signal proportional to the current i. a ct differs from a shunt in sensitivity and phase error. there should be an anti-aliasing lp filter inserted between the sensors and the inputs of both channels of the stpms1. internally, the differential voltage input related to the voltage channel is connected directly to the a/d converter, which implie s an amplification of x4. on the other side, the differential voltage input related to the current channel is connected first to a configurable x2 or x8 pre- amplifier and the output of this pre-amplifier to the similar a/d converter (x4 gain), which implies selectable pre-amplification of x8 or x32 and uses the same reference voltage. a pair of digital inputs (ms0 and ms1) is used to configure the device. 8.2 function description of the analog part the supply pins for the analog part are v cc , v dd , v ddac , v ddav , v ddd , and gnd. the gnd pin also represents a reference point. the v dd is an analog i/o pin of an internal +3.0 v low-drop voltage regulator, the v ddac and v ccav are the modulators supply inputs, while the v ddd is the digital front-end supply input. a 100 nf capacitor should be connected between v ddxx and gnd. the input of the mentioned regulator is v cc which powers also a band-gap, and bias generators. the analog part consists of several modules: band-gap reference and bias generators +3 v low-drop regulator two dc buffer amplifiers two ? ad converters control signal module
theory of operation stpms1 16/23 doc id 16524 rev 2 the band-gap voltage reference is used as the reference level source for the low-drop module and for the ad converters. this module produces several bias currents and voltages for all other analog modules. the low-drop regulator generates the +3.0 v power supply level. this level is used to power the dc buffers, pre-amplifier, and ad converter pair in the analog part of the device and whole digital part. it is brought out as v dd for external connections. as part of low-drop, there is a power on reset (por) detection circuit, which blocks all functions of the stpms1 by asserting the reset condition whenever a v cc supply level is less than +2.5 v. in order to enable proper operation of the switched capacitor (sc) section of ad converters, two dc buffers are added to the device. one is buffering the voltage reference level and the other is buffering the level of value equal to (vdd-vss)/2. the ad converter block is further split into a voltage and current channel. each channel consists of a differential pre-amplifier, sc integrator, comparator, amplifier bias block, and all necessary switches. the voltage channel sc integrator has a gain of 2 and there is no pre- amplifier block. the current channel sc integrator has a gain of 2 or 8, which can be selected by ms0 input, and has a pre-amplifier with a gain of 4. the amplitude of the input signal to the ad converter block must be kept less than 0.45 v ref . the output of each channel is input to the digital module as ? stream. for the operation of the analog part, a set of five clock signals is provided from the digital module. these signals derive from the clk signal. two of them are used to run the conversion, the next one is used as the chopper signal for the voltage channel and the last two are used as chopper signals for the current channel. all these signals are connected to the control signal module, which consists of standard digital cells powered from an analog supply. it produces all the necessary signals and switch controls of the ad converters. figure 17. power supply external connection scheme am07836v1 vdd gnd vdd gnd ms0 vdd ms1 vdd vcc datn clk dat vin cin cip vip gnd analog supply 3.3 -5.0v 100uf 100nf 100nf am07836v1 vdd gnd vdd gnd ms0 vdd ms1 vdd vcc datn clk dat vin cin cip vip gnd analog supply 3.3 -5.0v 100uf 100nf 100nf
stpms1 theory of operation doc id 16524 rev 2 17/23 8.3 functional description of the digital part a digital part is made up of: clock generator mode decoder time multiplex the clock generator produces all five clocks for the analog module. the mode decoder ge nerates signals for controlling the temperature coeffi cient of the on- chip band-gap voltage reference and the amplification factor of the current channel, clock prescaler, and voltage channel enable. the multiplex combines both ? input signals for the analog module into one signal dat which drives differential outputs dat and datn according to: dat= if clk then bsv or else bsc datn = not(dat). figure 18. block diagram of the modulator am07837v1 am07837v1 table 7. modes of operation ms0 mode description 0 0 ampl = 8 1 1 ampl = 32 table 8. changing of band-gap voltage reference ms1 mode description 0 0 tc = 100 ppm/c clk 1 tc = 170 ppm/c nclk 2 tc = 125 ppm/c 1 3 tc = 190 ppm/c
package mechanical data stpms1 18/23 doc id 16524 rev 2 9 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions, and product status are available at www.st.com . ecopack is an st registered trademark.
stpms1 package mechanical data doc id 16524 rev 2 19/23 dim. mm. inch. min. typ. max. min. typ. max. a0. 8 00. 9 0 1.00 0.0 3 1 0.0 3 5 0.0 39 a1 0 0.05 0.002 a 3 0.20 0.00 8 b 0.1 8 0. 3 0 0.007 0.012 d2. 9 0 3 .00 3 .10 0.114 0.11 8 0.122 d2 1.50 1. 8 0 0.05 9 0.071 e 3 .00 0.11 8 e2 2. 9 0 3 .00 3 .10 0.114 0.11 8 0.122 e 0.50 0.020 l0. 3 0 0.50 0.012 0.020 qfn16 ( 3 x 3 mm.) mechanical data 7509604/c
package mechanical data stpms1 20/23 doc id 16524 rev 2 dim. mm. inch. min. typ. max. min. typ. max. a1 8 0 7.0 8 7 c 12. 8 1 3 .2 0.504 0.51 9 d 20.2 0.7 9 5 n60 2. 3 62 t 14.4 0.567 ao 3 . 3 0.1 3 0 bo 3 . 3 0.1 3 0 ko 1.1 0.04 3 po 4 0.157 p 8 0. 3 15 tape & reel qfnxx/dfnxx ( 3 x 3 mm.) mechanical data
stpms1 package mechanical data doc id 16524 rev 2 21/23 figure 19. qfn16 (3 x 3 mm) footprint recommended data
revision history stpms1 22/23 doc id 16524 rev 2 10 revision history table 9. document revision history date revision changes 23-oct-2009 1 initial release. 07-oct-2010 2 data brief header removed from the cover page.
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